1. Field of the Invention
The present invention relates to an apparatus and a method for increasing semiconductor device density. In particular, the present invention relates to a vertical multi-chip device using combined flip chip, wire bond, tape automated bonding ("TAB"), and leads over and under assembly techniques to achieve densely packaged semiconductor devices, and a method for producing such devices.
2. State of the Art
Definitions: The following terms and acronyms will be used throughout the application and are defined as follows:
BGA--Ball Grid Array: An array of minute solder balls disposed on an attachment surface of a semiconductor die wherein the solder balls are refluxed for simultaneous attachment and electrical communication of the semiconductor die to a printed circuit board. Conductive polymer balls or bumps may also be employed.
COB--Chip On Board: The techniques used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and TAB.
Flip Chip: A chip or die that has a pattern or array of terminations spaced around the active surface of the die for face down mounting of the die to a substrate.
Flip Chip Attachment: A method of attaching a semiconductor die to a substrate in which the die is inverted so that the connecting conductor pads on the face of the device are set on mirror-image pads on the substrate (such as a printed circuit board), and bonded by solder reflux or a conductive polymer curing.
Glob Top: A glob of encapsulant material (usually epoxy or silicone or a combination thereof) surrounding a semiconductor die in a COB assembly.
PGA--Pin Grid Array: An array of small pins extending substantially perpendicular from the major plane of a semiconductor die, wherein the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
SLICC--Slightly Larger than Integrated Circuit Carrier: An array of minute solder balls disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
TAB--Tape Automated Bonding. Conductive traces are formed on a dielectric film such as a polyimide (the structure also being termed a "flex circuit"), and the film is precisely placed to electrically connect die and a circuit board or leadframe through the traces. Multiple connections are simultaneously effected.
State-of-the-art COB technology generally consists of three semiconductor die to printed circuit board conductive attachment techniques: flip chip attachment, wirebonding, and TAB.
Flip chip attachment consists of attaching a semiconductor die, generally having a BGA, a SLICC or a PGA, to a printed circuit board. With the BGA or SLICC, the solder or other conductive ball arrangement on the semiconductor die must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The semiconductor die is bonded to the printed circuit board by refluxing the solder balls. With the PGA, the pin arrangement of the semiconductor die must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the semiconductor die is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the semiconductor die and the printed circuit board for environmental protection and to enhance the attachment of the die to the board.
Wirebonding and TAB attachment generally begins with attaching a semiconductor die to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, a plurality of bond wires are attached, one at a time, to each bond pad on the semiconductor die and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding--using a combination of pressure and ultrasonic vibration barsts to form a metallurgical cold weld; thermocompression bonding--using a combination of pressure and elevated temperature to form a weld; and thernosonic bonding--using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The die may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape such as a polyimide are attached to the bond pads on the semiconductor die and to corresponding lead or trace ends on the printed circuit board. A glob top encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination and to aid mechanical attachment of the assembly components.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. Greater integrated circuit density is primarily limited by the space or "real estate" available for mounting die on a substrate such as a printed circuit board. Conventional lead frame design inherently limits package density for a given die size because the die-attach paddle of the lead frame must be larger than the die to which it is bonded. The larger the die, the less relative space that remains around the periphery of the die-bonding pad for wire bonding. Furthermore, the inner lead ends on a lead frame provide anchor points for the leads when the leads and the die are encapsulated in plastic, as by transfer molding. The anchor points may be emphasized as lateral flanges or bends or kinks in the lead. Therefore, as the die size is increased in relation to a given package size, there is a corresponding reduction in the space (lateral depth) along the sides of the package for the encapsulating plastic which joins the top and bottom portions of the molded plastic body at the mold part line and anchors to the leads. As the leads are subjected to the normal stresses of trimming, forming and assembly operations, the encapsulating plastic may crack, which may destroy the package seal and substantially increase the probability of premature device failure.
A so-called "leads over chip" ("LOC") arrangement eliminates the die-attach paddle of the lead frame and supports the die by its active surface from the inner lead ends of the lead frame. This permits a wider variety of bond pad patterns on the die, extends the leads-to-encapsulant bond area and, with appropriate design parameters, can reduce the size of the packaged device for a given die size.
One method of increasing integrated circuit density is to stack dice vertically. U.S. Pat. No. 5,012,323 ("the '323 patent") issued Apr. 30, 1991 to Farnworth teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. The lower die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires. The lower die needs to be slightly larger than the upper die in order that the lower die bonding pads are accessible from above through an aperture in the lead frame such that gold wire connections can be made to the lead extensions. However, this arrangement has a major disadvantage from a production standpoint, since the different size dice require that different equipment produce the different dice or that the same equipment be switched over in different production runs to produce the different dice. Moreover, the lead frame design employed by Farnworth employs long conductor runs between the die and the exterior of the package, and the lead frame configuration is specialized and rather complex.
U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby discloses a "leads over chip" (LOC) configuration, wherein the inner lead ends of a standard dual-in-line package (DIP) lead frame configuration extend over and are secured to the upper (active) surface of the die through a dielectric layer. The bond wire length is thus shortened by placing the inner lead ends in closer proximity to a central row of die bond pads, and the lead extensions purportedly enhance heat transfer from the die. However, the Pashby LOC configuration, as disclosed, relates to mounting and bonding only a single die.
U.S. Pat. No. 5,239,198 issued Aug. 24, 1993 to Lin et al. teaches an overmolded semiconductor device which achieves a multiple chip module without increasing the size of a fully package device. A semiconductor device is fabricated by providing a substrate on which a pattern of conductive traces is provided on a surface of the substrate. One electronic component is interconnected to the pattern of conductive traces, and a packaged body is overmolded around the electronic component and a portion of the pattern of conductive traces which leave a portion of the pattern of conductive traces exposed. Solder balls are attached to the exposed conductive traces and edge leads are connected to the periphery of the substrate. Both the solder balls and the edge leads provide external electrical connections to the device.
U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball teaches a multiple stacked die device that contains up to four dies which does not exceed the height of current single die packages. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin-adhesive layers between the stack dies. However, Ball secures all of the dice to the same (upper) side of the lead frame, necessarily increasing bond wire length, even if some of the leads are bent upwardly. Moreover, Ball employs a die paddle to support the die stack, a technique which requires an extra die-attach step, and which increases the distance between the inner lead ends and even the lowermost die in the stack, resulting in longer bond wires.
U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. teaches a multichip module that contains stacked die devices, the terminals or bond pads of which are wirebonded to a substrate or to adjacent die devices.
U.S. Pat. No. 5,399,898 issued May 21, 1995 to Rostoker ("Rostoker") teaches multichip, multitier semiconductor arrangements based on single and double-sided flip-chips. FIGS. 3a and 3b of Rostoker illustrate the use of dice with electrical contact points on both the back and face surfaces of a die. Using these dice to form a stacked die package eliminates the need for wirebonding and thus reduces the size of the stacked die package. These dice are double-sided flip-chips wherein the internal circuitry provides the appropriate circuit traces. However, these double-sided flip-chips are expensive and difficult to manufacture.
U.S. Pat. No. 5,422,435 to Takiar et al. teaches stacked die having wire bonds extending to each other and to the leads of a carrier member such as a lead frame.
U.S. Pat. No. 5,471,369 to Honda et al. teaches stacked die package in which the dice are secured so as to prevent displacement by the encapsulant flow front during a transfer molding process. The package includes at least two stacked semiconductor chips with at least two leadframes and utilizing both bond wires and TAB to connect said chips to said leadframes.
See also U.S. Pat. Nos. 4,264,917; 5,147,815; 5,252,857; 5,331,235; 5,438,224; 5,483,024; 5,484,959 and Japanese Patent Documents 1-28856 (Takeuchi); 3-169062 (Goto); 56-62351 (Sano) and 62-126661 (Sakafa) for disclosures of various multi-chip semiconductor assemblies.
It would be advantageous to develop a technique and assembly for increasing integrated circuit density using non-customized die configurations in combination with commercially-available, widely-practiced semiconductor device fabrication techniques.